1. Field of the Invention
The present invention is related to digital sequential logic circuits. More particularly, the present invention presents a self-resetting flip-flop for use in high-speed electronics.
2. The Background Art
In high speed digital electronics, it is often desirable to have the output of one functional unit isolated from the input of the other, except at certain times.
FIG. 1 is a prior art example of isolating one functional unit from another using flip-flips.
Referring to FIG. 1, system 10 includes a device 12 which is coupled to an address bus 14. Memory manager 16 is coupled to address bus 14 and memory 18, and includes row circuitry 20 and column circuitry 22. Row circuitry 20 and column circuitry 22 each have similar circuitry which is used to access the memory cells corresponding to an address on the address bus. Thus, flip-flops 24, predecoder 26 and decoder 28 are each present in row circuitry 20 and column circuitry 22.
In order to provide the highest level of data throughput to and from memory, it is desirable to isolate activity on an address bus from address decoders, except at specific times when the address data is generally held to be valid.
In order to isolate the address bus from the decoder a flip-flop is often provided between the bus and the decoder. As is known by those of ordinary skill in the art, a flip-flop takes a data state present on its input and latches that data to its output, on the rising edge of a clock cycle.
In some cases, it is appropriate to reset the flip-flop output to a known "safe" state so that functional units using the data supplied by the flip-flop will always be receiving valid data.
Although prior art flip-flops are suitable for their intended purpose of providing a measure of isolation between the incoming data lines and the output lines, the reset mechanisms present in these flip-flops are often not fast enough to meet the demands of high speed electronics. It would therefore be beneficial to provide a flip-flop having a fast reset mechanism.